1. Field of the Invention
The present invention relates to a semiconductor integrated circuit.
2. Related Art
As the technology node of LSI advances and the switching speed is improved, defects caused by circuit operation, such as degradation of the contact caused between wiring and semiconductors and breaking of wiring, are of concern.
Diode transistor logic type circuits are also begun to be proposed as circuit architecture of the next generation (see, for example, A. DeHon, IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 2, NO. 1, P. 23, MARCH 2003). In that case as well, it is of concern that degradation in diodes or resistors might cause a fault in circuit operation.
As a method for providing resistance against errors in circuit signals, a method of preparing some same circuits to provide redundancy and detecting and correcting an operation fault by comparing outputs of the circuits is widely used (see, for example, JP-A 2003-177935 (KOKAI)).
In this method, however, only a result of occurrence of an operation fault is detected, but it is impossible to inspect a state in which a circuit is being degraded. As for the cause of the operation fault, it cannot be discriminated whether it is an error caused occasionally by noise or whether it is an operation fault caused by device degradation. If the operation fault is caused by device degradation, it cannot be detected that delays in the circuit increase and timing margin is lost. As a result, it cannot be judged whether replacement of the circuit itself is needed or whether reconstruction of the circuit is necessary in a programmable circuit such as an FPGA (Field Programming Gate Array).